1. Field of the Invention
The present invention relates to the process of verifying a hardware design to ensure that it operates correctly. More specifically, the present invention relates to a method and an apparatus for facilitating structural coverage of a design during a design verification process.
2. Related Art
Verification techniques which are presently used to ensure the functional correctness of integrated circuits do not scale with the complexity of circuit designs. For instance, because of the non-linear nature of state machines, increasing the complexity of a design can lead to an exponential increase in the verification complexity. For example, each additional state element in a state machine doubles the size of the state-space to be verified. However, despite increasing verification complexity, design correctness still must be verified to ensure that designs operate correctly.
Design verification techniques attempt to determine whether a design-under-test (DUT) will operate correctly. In particular, commonly-used assertion-based verification techniques operate by sprinkling “monitoring points,” or “assertions,” throughout the design description in the hope of detecting violations during design simulation. While designers can build assertions and test cases to cover every aspect of the design, this manual process is extremely time-consuming.
To reduce the amount of human time involved in the verification process, many simulation tools attempt to use random input patterns to achieve a target “coverage” for a design. For instance, achieving the target coverage can involve executing a certain percentage of the statements, branch conditions, and/or execution paths in the design. Designers seek to attain “coverage convergence,” or a reasonable level of certainty that an acceptable subset of the design has been tested. To minimize the cost of achieving coverage convergence, “formal tools” that incorporate mathematically-based techniques are often used to automatically explore the state space in a formal manner.
While existing assertion-based verification techniques partially automate the verification process, they do so by modifying the hardware description to include assertions, which may cause design changes and/or pollution. Furthermore, while an assertion violation proves that the design is not correct, proving design correctness is intractable, and there is no way to determine a “reasonable” testing timeframe that will flush out most of the design bugs. An additional limitation is that current coverage techniques are implemented using simulation techniques that do not leverage the formal verification techniques typically employed for model checking.
Hence, what is needed is a method and an apparatus for verifying a design that achieves high levels of structural coverage of the design without the above-described problems.